Integrated circuits (ICs) on a chip are prevalent in a variety of applications and electronic devices. Increasing demands are made to fabricate ICs with larger numbers of circuit elements at higher densities and smaller line widths. Signal coupling and noise issues are becoming a major concern in areas such as, system-on-chip (SOC), due to high integration. Undesired simultaneous switching (SS) events can arise in a chip package where one or more drivers on a data bus switch states at the same time. In one example model of a 64-bit bus, if many drivers switch from high to low at the same time there can be a large current surge. Any output remaining high and internal logic circuitry may see a large voltage dip. The switching of many outputs from high to low can also cause capacitance on the outputs to discharge to ground causing a voltage rise in any low state outputs. A sufficiently large ‘power bounce’ or ground bounce’ can cause false switching and logic errors. See, William D. Brown, ed., Advanced Electronic Packaging with Emphasis on Multichip Modules (IEEE Press: New York, N.Y. 1999), pp. 174-175.
Such simultaneous switching can cause current/resistance (IR) drop and ground bounce. IC performance can be degraded. Among other things, IR drop (or power drop) can cause more power to be drawn from a power supply and adversely affect timing. Ground bounce from false switching of a gate is difficult and time consuming to debug. Unfortunately, simultaneous switching can occur in sub-micron technology (e.g., at about 0.18 micron) and will worsen as IC fabrication proceeds to deep sub-micron technology (e.g, 0.13 micron-0.9 micron or below) where circuit elements are even more sensitive.
Testers face present special challenges trying to isolate points of failure in an IC arising from simultaneous switching. Failure is usually extremely random and hard to replicate during testing. Some stations on an IC fail, while others do not fail. Some stations may take several days to fail. Some applications or streams being processed by an IC may fail, while others being handled by the same chip do not fail. Finally, the failure may even be inconsistent.
Conventional testing approaches to SS are limited. Often a time consuming process of varying voltage, temperature, and running a chip overnight with testing by different devices are required. Internal signals may not be directly observable and require expensive focused ion beam (FIB) approaches to debug. State of the art electronic design application (EDA) tools are not capable of detecting dynamic IR drop or noise coupling resulting from SS. Due to the random failure nature of SS, a user usually reports a problem to a manufacturer at a very late stage. For example, this may be reported after a chip is installed in a set-top box or video graphics card. This makes it even harder for a manufacturer to test since it is hard to develop test software or modify programs on the user's platform. For instance, a legal process may have to be followed to gain access to a user's source code, environmental issues need to be resolved to compile and build software, and it is difficult to port a user's a test program to a manufacturer's reference board. As result, a SS failure is often a high priority that requires urgent coordinated effort by engineers of both users and manufacturers to handle. This is costly and disruptive.
What is needed is a testing approach that allows testing for simultaneous switching within hardware to be carried out in a manner which is faster, simpler, and more effective than conventional techniques. A testing approach that allows testing for simultaneous switching within hardware to be carried out selectively on demand even prior to release of a chip is needed.